1. Field of the Invention
This invention relates generally to a sense amplifier for an integrated circuit memory, and, more particularly, to a sense amplifier for a static random access memory (SRAM).
2. Description of the Related Art
Modern integrated circuit memory devices generally include high density memory arrays on the integrated circuit chip. The array contains many memory cells, each of which stores a bit of data. In dynamic random access memories (DRAMs), for example, each of the memory cells stores an electrical charge, the value of the electrical charge being indicative of the logical bit value stored in the cell. The absence of an electrical charge in the memory cell may indicate a logical 0, whereas the presence of an electrical charge in the memory cell may indicate a logical 1. In static random access memories (SRAMs), a memory cell may have two parts, a first part storing the logical value and the second part storing the logical complement.
The many memory cells in an integrated circuit memory device are typically arranged in an array having a number of intersecting rows and columns. One memory cell is normally associated with each intersection of a row and a column. Word lines, which correspond to rows in the array, are used to access the memory cells connected to that word line. Bit lines or complementary bit line pairs, which correspond to columns in the array, are used to interconnect memory cells to sense amplifiers where the presence or absence of an electrical charge in the memory cell can be detected. Row decoders and column decoders activate a selected word line and a selected bit line or bit line pair to access a particular memory cell as designated by an address input to the memory device.
As memory device technology has advanced, memory cells have generally become smaller, and the amount of electrical charge that can be stored in the cell has diminished. Consequently, the electrical charge differential between a logical 0 and a logical 1 has diminished. In addition, as memory arrays have grown larger, bit lines have grown longer, the number of memory cells coupled to a bit line has increased, and the capacitances associated with the bit lines have increased. As a result, when a memory cell is accessed so that its contents may be read, the charge or voltage differential it will induce on a pair of bit lines becomes very small. To detect this charge differential and thereby read the logical value stored in the memory cell, latching sense amplifiers have become commonplace.
In a general sense, a latching sense amplifier compares the charge on a bit line with the charge on what is commonly known as a complementary bit line and amplifies that differential. As the charge differential between a bit line and its associated complementary bit line grows smaller, the detection of that differential and the amplification of it becomes slower and less reliable. There is a need for sense amplifiers that can more quickly and more reliably read the contents of a particular memory cell notwithstanding the very small electrical charges associated with the memory cell.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.